Here's how I made the switch.
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The lessons learned from the FPGA study also carried over to the ASIC flow. After pushing the code base through the same toolchain used to generate the Baochip-1x, the gate count and delays were similarly large and “slow”. I use “slow” in quotes because it’s still plenty fast for what it needs to do – bit banging GPIO – it’s just slow compared to what you could do in an ASIC.